10 search results - page 1 / 2 » Cache Configuration Exploration on Prototyping Platforms |
RSP
2003
IEEE
13 years 10 months ago
2003
IEEE
We describe cache architecture, intended for prototype-oriented IC platforms, that automatically finds the best cache configuration for a particular application. The cache itself ...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
TCAD
2002
13 years 4 months ago
2002
System-on-a-chip (SOC) platform manufacturers are increasingly adding configurable features that provide power and performance flexibility in order to increase a platform's ap...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
In current Chip-multiprocessors (CMPs), a significant portion of the die is consumed by the last-level cache. Until recently, the balance of cache and core space has been primari...