10 search results - page 2 / 2 » Cache Filtering Techniques to Reduce the Negative Impact of ... |
ISCA
1994
IEEE
13 years 9 months ago
1994
IEEE
Multithreaded architectures context switch between instruction streams to hide memory access latency. Although this improves processor utilization, it can increase cache interfere...
LCTRTS
2009
Springer
14 years 3 days ago
2009
Springer
Instruction fetch behavior has been shown to be very regular and predictable, even for diverse application areas. In this work, we propose the Lookahead Instruction Fetch Engine (...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
CF
2004
ACM
13 years 10 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
RTAS
1996
IEEE
13 years 9 months ago
1996
IEEE
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching, which is necessa...