107 search results - page 22 / 22 » Cache Sharing Management for Performance Fairness in Chip Mu... |
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
In order to extract high levels of performance from modern parallel architectures, the effective management of deep memory hierarchies is very important. While architectural advan...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
With the recent design shift towards increasing the number of processing elements in a chip, high-bandwidth support in on-chip interconnect is essential for low-latency communicat...