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ISPASS
2005
IEEE
13 years 11 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
MASCOTS
2001
13 years 6 months ago
Simulation Evaluation of a Heterogeneous Web Proxy Caching Hierarchy
This paper uses trace-driven simulations to evaluate the performance of different cache management techniques for multi-level Web proxy caching hierarchies. In particular, the exp...
Mudashiru Busari, Carey L. Williamson
ISCAPDCS
2004
13 years 6 months ago
One-Level Cache Memory Design for Scalable SMT Architectures
The cache hierarchy design in existing SMT and superscalar processors is optimized for latency, but not for bandwidth. The size of the L1 data cache did not scale over the past de...
Muhamed F. Mudawar, John R. Wani
ISLPED
1997
ACM
114views Hardware» more  ISLPED 1997»
13 years 9 months ago
Analysis of power consumption in memory hierarchies
In this paper, we note and analyze a key trade-off: as the complexity of caches increases (higher set-associativity, larger block size, and larger overall size), the power consume...
Patrick Hicks, Matthew Walnock, Robert Michael Owe...