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DATE
2009
IEEE
81views Hardware» more  DATE 2009»
14 years 4 days ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos
EUROSYS
2011
ACM
12 years 8 months ago
Scarlett: coping with skewed content popularity in mapreduce clusters
To improve data availability and resilience MapReduce frameworks use file systems that replicate data uniformly. However, analysis of job logs from a large production cluster show...
Ganesh Ananthanarayanan, Sameer Agarwal, Srikanth ...
RSP
2003
IEEE
103views Control Systems» more  RSP 2003»
13 years 10 months ago
An Instruction Throughput Model of Superscalar Processors
With advances in semiconductor technology, processors are becoming larger and more complex. Future processor designers will face an enormous design space, and must evaluate more a...
Tarek M. Taha, D. Scott Wills
MICRO
2002
IEEE
118views Hardware» more  MICRO 2002»
13 years 10 months ago
Exploiting data-width locality to increase superscalar execution bandwidth
In a 64-bit processor, many of the data values actually used in computations require much narrower data-widths. In this study, we demonstrate that instruction data-widths exhibit ...
Gabriel H. Loh
HPCA
1999
IEEE
13 years 9 months ago
A Study of Control Independence in Superscalar Processors
Control independence has been put forward as a significant new source of instruction-level parallelism for future generation processors. However, its performance potential under p...
Eric Rotenberg, Quinn Jacobson, James E. Smith