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» Challenges in Physical Chip Design
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DAC
2002
ACM
14 years 6 months ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge
CISIS
2009
IEEE
14 years 4 days ago
Designing Regular Network-on-Chip Topologies under Technology, Architecture and Software Constraints
—Regular multi-core processors are appearing in the embedded system market as high performance software programmable solutions. The use of regular interconnect fabrics for them a...
Francisco Gilabert Villamón, Daniele Ludovi...
ISLPED
2005
ACM
100views Hardware» more  ISLPED 2005»
13 years 11 months ago
Joint exploration of architectural and physical design spaces with thermal consideration
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout....
Yen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen ...
SLIP
2006
ACM
13 years 11 months ago
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
— The increasing gap between design productivity and chip complexity and the emerging Systems-On-Chip (SOC) architectural template have led to the wide utilization of reusable ha...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
ICCAD
2003
IEEE
138views Hardware» more  ICCAD 2003»
14 years 2 months ago
Multi-Million Gate FPGA Physical Design Challenges
The recent past has seen a tremendous increase in the size of design circuits that can be implemented in a single FPGA. These large design sizes significantly impact cycle time du...
Maogang Wang, Abhishek Ranjan, Salil Raje