28 search results - page 2 / 6 » Challenges in clockgating for a low power ASIC methodology |
HPCA
2003
IEEE
14 years 5 months ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
The implementation of interconnect is becoming a significant challenge in modern IC design. Both synchronous and asynchronous strategies have been suggested to manage this problem...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
DAC
2003
ACM
14 years 6 months ago
2003
ACM
A low power wireless intercom system is designed and implemented. Two fully-operational ASICs, integrating custom and commercial IP, implement the entire digital portion of the pr...
ISQED
2009
IEEE
14 years 3 days ago
2009
IEEE
- Designing a power-gating structure with high performance in the active mode and low leakage and short wakeup time during standby mode is an important and challenging task. This p...