280 search results - page 56 / 56 » Challenges in exploitation of loop parallelism in embedded a... |
ASPLOS
2010
ACM
14 years 19 days ago
2010
ACM
To make efficient use of CMPs with tens to hundreds of cores, it is often necessary to exploit fine-grain parallelism. However, managing tasks of a few thousand instructions is ...
HPCA
2009
IEEE
14 years 6 months ago
2009
IEEE
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
ICMCS
2000
IEEE
13 years 10 months ago
2000
IEEE
The coming millenium will be characterized by the availability of multiple information appliances that make ubiquitous information access an accepted fact of life. The ability to ...
SC
1992
ACM
13 years 9 months ago
1992
ACM
We are currently developing Willow, a shared-memory multiprocessor whose design provides system capacity and performance capable of supporting over a thousand commercial microproc...
DAC
2010
ACM
13 years 9 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...