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TCAD
1998
81views more  TCAD 1998»
13 years 4 months ago
Characterization and parameterized generation of synthetic combinational benchmark circuits
Michael D. Hutton, Jonathan Rose, Jerry P. Grossma...
FPGA
1997
ACM
145views FPGA» more  FPGA 1997»
13 years 9 months ago
Generation of Synthetic Sequential Benchmark Circuits
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
TCAD
2002
145views more  TCAD 2002»
13 years 4 months ago
Automatic generation of synthetic sequential benchmark circuits
The design of programmable logic architectures and supporting computer-aided design tools fundamentally requires both a good understanding of the combinatorial nature of netlist gr...
Michael D. Hutton, Jonathan Rose, Derek G. Corneil
ISPD
1999
ACM
98views Hardware» more  ISPD 1999»
13 years 9 months ago
Towards synthetic benchmark circuits for evaluating timing-driven CAD tools
For the development and evaluation of CAD-tools for partitioning, floorplanning, placement, and routing of digital circuits, a huge amount of benchmark circuits with suitable cha...
Dirk Stroobandt, Peter Verplaetse, Jan Van Campenh...
DATE
1999
IEEE
194views Hardware» more  DATE 1999»
13 years 9 months ago
Algorithms for Solving Boolean Satisfiability in Combinational Circuits
Boolean Satisfiability is a ubiquitous modeling tool in Electronic Design Automation, It finds application in test pattern generation, delay-fault testing, combinational equivalen...
Luís Guerra e Silva, Luis Miguel Silveira, ...