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BMCBI
2005
246views more  BMCBI 2005»
13 years 5 months ago
ParPEST: a pipeline for EST data analysis based on parallel computing
Background: Expressed Sequence Tags (ESTs) are short and error-prone DNA sequences generated from the 5' and 3' ends of randomly selected cDNA clones. They provide an im...
Nunzio D'Agostino, Mario Aversano, Maria Luisa Chi...
ICCD
2007
IEEE
105views Hardware» more  ICCD 2007»
14 years 3 days ago
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits
A methodology for constructing circuit-level mismatch models and performing yield optimization is presented for CMOS analog circuits. The methodology combines statistical techniqu...
Mingjing Chen, Alex Orailoglu
ISSS
1996
IEEE
169views Hardware» more  ISSS 1996»
13 years 10 months ago
The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems
The application range of the embedded computing is going to cover the majority of the market products spanning from consumer electronic, automotive, telecom and process control. F...
Alessandro Balboni, William Fornaciari, M. Vincenz...
ISLPED
2009
ACM
123views Hardware» more  ISLPED 2009»
13 years 10 months ago
Predict and act: dynamic thermal management for multi-core processors
In this paper, we propose a proactive dynamic thermal management scheme for chip multiprocessors that run multi-threaded workloads. We introduce a new predictor that utilizes the ...
Raid Zuhair Ayoub, Tajana Simunic Rosing
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
13 years 12 months ago
Soft delay error analysis in logic circuits
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
Balkaran S. Gill, Christos A. Papachristou, Franci...