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» ChipViz : Visualizing Memory Chip Test Data
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DELTA
2002
IEEE
13 years 10 months ago
Address and Data Scrambling: Causes and Impact on Memory Tests
: The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a lar...
A. J. van de Goor, Ivo Schanstra
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
13 years 12 months ago
Optimized integration of test compression and sharing for SOC testing
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
BMCBI
2011
13 years 16 days ago
The dChip survival analysis module for microarray data
Background: Genome-wide expression signatures are emerging as potential marker for overall survival and disease recurrence risk as evidenced by recent commercialization of gene ex...
Samir B. Amin, Parantu K. Shah, Aimin Yan, Sophia ...
ICCD
1999
IEEE
93views Hardware» more  ICCD 1999»
13 years 9 months ago
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...
Abhijit Jas, Nur A. Touba
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
13 years 11 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...