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» Circuit simulation based obstacle-aware Steiner routing
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DAC
2003
ACM
13 years 10 months ago
Fast timing-driven partitioning-based placement for island style FPGAs
In this paper we propose a partitioning-based placement algorithm for FPGAs. The method incorporates simple, but effective heuristics that target delay minimization. The placement...
Pongstorn Maidee, Cristinel Ababei, Kia Bazargan
ICDCS
2006
IEEE
13 years 11 months ago
GMP: Distributed Geographic Multicast Routing in Wireless Sensor Networks
In this paper, we propose a novel Geographic Multicast routing Protocol (GMP) for wireless sensor networks1 . The proposed protocol is fully distributed and stateless. Given a set...
Shibo Wu, K. Selçuk Candan
ICRA
2010
IEEE
172views Robotics» more  ICRA 2010»
13 years 3 months ago
Coordinated multi-robot real-time exploration with connectivity and bandwidth awareness
— While there has been substantial progress for multi-robot exploration of an unknown area, little attention has been given to communication, especially bandwidth constraints in ...
Yuanteng Pei, Matt W. Mutka, Ning Xi
GLVLSI
2009
IEEE
128views VLSI» more  GLVLSI 2009»
13 years 9 months ago
Impact of lithography-friendly circuit layout
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...
Pratik J. Shah, Jiang Hu
ASPDAC
2005
ACM
98views Hardware» more  ASPDAC 2005»
13 years 7 months ago
Process variation robust clock tree routing
As the minimum feature sizes of VLSI circuits get smaller while the clock frequency increases, the effects of process variations become significant. We propose a UST/DME based ap...
Wai-Ching Douglas Lam, Cheng-Kok Koh