45 search results - page 8 / 9 » Circuit simulation based obstacle-aware Steiner routing |
CORR
1998
Springer
13 years 4 months ago
1998
Springer
Abstract In this paper we describe a hands-on laboratory oriented instructional package that we have developed for data communications and networking. The package consists of a sof...
DAC
2002
ACM
14 years 5 months ago
2002
ACM
The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction i...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
While performance specifications are verified before sign-off for a modern nanometer scale design, extensive application of optical proximity correction substantially alters the l...
ISPD
2005
ACM
13 years 10 months ago
2005
ACM
In this paper, the problem of bus-driven floorplanning is addressed. Given a set of blocks and the bus specification (the width of each bus and the blocks that the bus need to g...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
As process technology migrates to deep submicron with feature size less than 100nm, global wire delay is becoming a major hindrance in keeping the latency of intra-chip communicat...