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» Circuits for wide-window superscalar processors
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ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
13 years 9 months ago
Circuits for wide-window superscalar processors
Our program benchmarks and simulations of novel circuits indicate that large-window processors are feasible. Using our redesigned superscalar components, a large-window processor ...
Dana S. Henry, Bradley C. Kuszmaul, Gabriel H. Loh...
DSN
2007
IEEE
13 years 11 months ago
Superscalar Processor Performance Enhancement through Reliable Dynamic Clock Frequency Tuning
Synchronous circuits are typically clocked considering worst case timing paths so that timing errors are avoided under all circumstances. In the case of a pipelined processor, thi...
Viswanathan Subramanian, Mikel Bezdek, Naga Durga ...
ISLPED
2003
ACM
95views Hardware» more  ISLPED 2003»
13 years 10 months ago
Power efficient comparators for long arguments in superscalar processors
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...
Dmitry Ponomarev, Gurhan Kucuk, Oguz Ergin, Kanad ...
MST
2002
107views more  MST 2002»
13 years 4 months ago
A Comparison of Asymptotically Scalable Superscalar Processors
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path lengths of many components...
Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh
CF
2005
ACM
13 years 6 months ago
An efficient wakeup design for energy reduction in high-performance superscalar processors
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
Kuo-Su Hsiao, Chung-Ho Chen