31 search results - page 3 / 7 » Circuits with arbitrary gates for random operators |
FOCS
2007
IEEE
13 years 9 months ago
2007
IEEE
We develop a new technique of proving lower bounds for the randomized communication complexity of boolean functions in the multiparty `Number on the Forehead' model. Our meth...
WEA
2010
Springer
14 years 7 days ago
2010
Springer
Abstract. A new technique for combinational logic optimization is described. The technique is a two-step process. In the first step, the nonlinearity of a circuit – as measured ...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. T...
ECCC
2000
13 years 5 months ago
2000
This article initiates a rigorous theoretical analysis of the computational power of circuits that employ modules for computing winner-take-all. Computational models that involve ...
ASPDAC
2009
ACM
14 years 8 days ago
2009
ACM
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...