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Clock Period Minimization of Semi-Synchronous Circuits by Ga...
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Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion
13 years 9 months ago
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www.lab.ss.titech.ac.jp
Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani
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DAC
2005
ACM
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Computer Architecture
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Race-condition-aware clock skew scheduling
14 years 5 months ago
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rd.cycu.edu.tw
The race conditions often limit the smallest feasible clock period that the optimal clock skew scheduling can achieve. Therefore, the combination of clock skew scheduling and dela...
Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu
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