9 search results - page 1 / 2 » Clock Skew Evaluation Considering Manufacturing Variability ... |
ISQED
2008
IEEE
13 years 11 months ago
2008
IEEE
Influence of manufacturing variability on circuit performance has been increasing because of finer manufacturing process and lowered supply voltage. In this paper, we focus on m...
GLVLSI
2010
IEEE
13 years 9 months ago
2010
IEEE
This paper presents a self-compensation scheme of manufacturing variability for clock skew reduction. In the proposed scheme, a CDN with embedded variability sensors tunes variabl...
ISQED
2005
IEEE
13 years 10 months ago
2005
IEEE
This paper discusses clock skew due to manufacturing variability and environmental change. In clock tree design, transition time constraint is an important design parameter that c...
ISQED
2007
IEEE
13 years 11 months ago
2007
IEEE
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
ICCAD
1993
IEEE
13 years 9 months ago
1993
IEEE
We have proposed an e cient measure to reduce the clock skew by assigning the clock network with variable branch widths. This measure has long been used for \H" clock tree. T...