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» Clock gating architectures for FPGA power reduction
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DATE
2009
IEEE
107views Hardware» more  DATE 2009»
14 years 5 months ago
Learning early-stage platform dimensioning from late-stage timing verification
— Today's innovations in the automotive sector are, to a great extent, based on electronics. The increasing integration complexity and stringent cost reduction goals turn E/...
Kai Richter, Marek Jersak, Rolf Ernst
NOCS
2009
IEEE
14 years 5 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
DSD
2002
IEEE
96views Hardware» more  DSD 2002»
14 years 3 months ago
Networks on Silicon: Blessing or Nightmare?
Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution, and signal integrity. Those ...
Paul Wielage, Kees G. W. Goossens
TC
2008
13 years 10 months ago
Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations
This paper examines the hardware implementation trade-offs when evaluating functions via piecewise polynomial approximations and interpolations for precisions of up to 24 bits. In ...
Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. V...
NIXDORF
1992
116views Hardware» more  NIXDORF 1992»
14 years 2 months ago
Programmable Active Memories: A Performance Assessment
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
Patrice Bertin, Didier Roncin, Jean Vuillemin