7 search results - page 1 / 2 » Clock power reduction for virtex-5 FPGAs |
FPGA
2009
ACM
13 years 11 months ago
2009
ACM
Clock network power in field-programmable gate arrays (FPGAs) is considered and two complementary approaches for clock power reduction in the Xilinx R VirtexTM -5 FPGA are presen...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
ICCAD
2005
IEEE
14 years 1 months ago
2005
IEEE
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Modern FPGA architectures provide ample routing resources so that designs can be routed successfully. The routing architecture is designed to handle versatile connection configur...