96 search results - page 2 / 20 » Clock-Aware Placement for FPGAs |
DAC
1994
ACM
13 years 9 months ago
1994
ACM
Sequential place and route tools for FPGAs are inherently weak at addressing both wirability and timing optimizations. This is primarily due to the difficulty in predicting these ...
FPGA
2000
ACM
13 years 9 months ago
2000
ACM
In this paper, we study the technology mapping problem for a novel FPGA architecture that is based on k-input single-output PLA-like cells, or, k/m-macrocells. Each cell in this a...
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
The demand for high-speed FPGA compilation tools has occurred for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing h...
JCP
2008
13 years 5 months ago
2008
Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots...
FPGA
1998
ACM
13 years 9 months ago
1998
ACM