217 search results - page 2 / 44 » Closed-Form Simulation and Robustness Models for SEU-Toleran... |
CORR
2011
Springer
12 years 8 months ago
2011
Springer
Abstract—Coping with outliers contaminating dynamical processes is of major importance in various applications because mismatches from nominal models are not uncommon in practice...
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
Logical effort (LE) is a linear technique for modelling the delay of a circuit in a technology independent manner. It offers the potential to simplify delay models for FPGAs and g...
DAC
1999
ACM
14 years 5 months ago
1999
ACM
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ISCAS
1999
IEEE
13 years 9 months ago
1999
IEEE
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
ICRA
2008
IEEE
13 years 11 months ago
2008
IEEE
— In this paper we present a novel approach to robust visual servoing. This method removes the feature tracking step from a typical visual servoing algorithm. We do not need corr...