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ICCAD
2005
IEEE
151views Hardware» more  ICCAD 2005»
14 years 2 months ago
Architecture and details of a high quality, large-scale analytical placer
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
Andrew B. Kahng, Sherief Reda, Qinke Wang
DAC
2003
ACM
14 years 6 months ago
Multilevel floorplanning/placement for large-scale modules using B*-trees
We present in this paper a multilevel floorplanning/placement framework based on the B*-tree representation, called MB*-tree, to handle the floorplanning and packing for large-sca...
Hsun-Cheng Lee, Yao-Wen Chang, Jer-Ming Hsu, Hanna...
PLDI
1999
ACM
13 years 9 months ago
Cache-Conscious Structure Layout
Hardware trends have produced an increasing disparity between processor speeds and memory access times. While a variety of techniques for tolerating or reducing memory latency hav...
Trishul M. Chilimbi, Mark D. Hill, James R. Larus
ISPD
2005
ACM
239views Hardware» more  ISPD 2005»
13 years 10 months ago
Mapping algorithm for large-scale field programmable analog array
Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With thes...
I. Faik Baskaya, Sasank Reddy, Sung Kyu Lim, Tyson...