8 search results - page 2 / 2 » Cluster-aware iterative improvement techniques for partition... |
TCAD
2010
13 years 15 days ago
2010
Design debugging is a major bottleneck in modern VLSI design flows as both the design size and the length of the error trace contribute to its inherent complexity. With typical des...
DAC
2005
ACM
13 years 7 months ago
2005
ACM
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
GLVLSI
2009
IEEE
14 years 15 days ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...