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» Co-design of interleaved memory systems
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ARITH
1993
IEEE
13 years 9 months ago
An accurate LNS arithmetic unit using interleaved memory function interpolator
This paper describes a logarithmic number system (LNS) arithmetic unit using a new methodfor polynomial interpolation in hardware. The use of an interleaved memory reduces storage...
David M. Lewis
ICC
2007
IEEE
138views Communications» more  ICC 2007»
13 years 11 months ago
Scalable Router Memory Architecture Based on Inter-leaved DRAM: Analysis and Numerical Studies
1  Routers need buffers to store and forward packets, especially when there is network congestion. With current memory technology, neither the SRAM nor the DRAM alone is suitabl...
Feng Wang, Mounir Hamdi
HPCA
2012
IEEE
12 years 13 days ago
Balancing DRAM locality and parallelism in shared memory CMP systems
Modern memory systems rely on spatial locality to provide high bandwidth while minimizing memory device power and cost. The trend of increasing the number of cores that share memo...
Min Kyu Jeong, Doe Hyun Yoon, Dam Sunwoo, Mike Sul...
CODES
2000
IEEE
13 years 9 months ago
Frequency interleaving as a codesign scheduling paradigm
Frequency interleaving is introduced as a means of conceptualizing and co-scheduling hardware and software behaviors so that software models with conceptually unbounded state and ...
JoAnn M. Paul, Simon N. Peffers, Donald E. Thomas
MICRO
2008
IEEE
109views Hardware» more  MICRO 2008»
13 years 11 months ago
Dependence-aware transactional memory for increased concurrency
—Transactional memory (TM) is a promising paradigm for helping programmers take advantage of emerging multicore platforms. Though they perform well under low contention, hardware...
Hany E. Ramadan, Christopher J. Rossbach, Emmett W...