624 search results - page 2 / 125 » Co-optimization of Performance and Power in a Superscalar Pr... |
TCAD
2010
13 years 1 hour ago
2010
Abstract--In sub-100 nm CMOS processes, delay and leakage power reduction continue to be among the most critical design concerns. We propose to exploit the recent availability of f...
MICRO
2002
IEEE
13 years 10 months ago
2002
IEEE
Multimedia processing on embedded devices requires an architecture that leads to high performance, low power consumption, reduced design complexity, and small code size. In this p...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
High performance processors use checkpointing to rapidly recover from branch mispredictions and possibly other exceptions. We demonstrate that conventional checkpointing becomes u...
ISCA
2002
IEEE
13 years 10 months ago
2002
IEEE
Due to shrinking technologies and increasing design sizes, it is becoming more difficult and expensive to distribute a global clock signal with low skew throughout a processor di...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
Traditional pulldown comparators that are used to implement associativeaddressing logic in superscalar microprocessors dissipate energy on a mismatch in any bit position in the co...