18 search results - page 3 / 4 » Coarse-Grain Pipelining on Multiple FPGA Architectures |
FPL
2003
Springer
13 years 10 months ago
2003
Springer
In this paper we present a single-chip FPGA full encryptor/decryptor core design of the AES algorithm. Our design performs all of them, encryption, decryption and key scheduling pr...
ESANN
2006
13 years 6 months ago
2006
Abstract. Despite several previous studies, little progress has been made in building successful neural systems for image segmentation in digital hardware. Spiking neural networks ...
RECONFIG
2008
IEEE
13 years 11 months ago
2008
IEEE
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
EGH
2004
Springer
13 years 10 months ago
2004
Springer
Realtime ray tracing has recently established itself as a possible alternative to the current rasterization approach for interactive 3D graphics. However, the performance of exist...
FPGA
2004
ACM
13 years 10 months ago
2004
ACM
We present a cryptographic architecture optimization technique called divide-and-concatenate based on two observations: (i) the area of a multiplier and associated data path decre...