13 search results - page 2 / 3 » Combining Instruction Coding and Scheduling to Optimize Ener... |
LCTRTS
2001
Springer
13 years 9 months ago
2001
Springer
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
ICS
1995
Tsinghua U.
13 years 8 months ago
1995
Tsinghua U.
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
ISCAS
2005
IEEE
13 years 10 months ago
2005
IEEE
— Architectures based on Very Long Instruction Word (VLIW) processors are an optimal choice in the attempt to obtain high performance levels in mobile devices. The effectiveness ...
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
The market demand for portable multimedia applications has exploded in the recent years. Unfortunately, for such applications current compilers and software optimization methods o...
GLVLSI
2005
IEEE
13 years 10 months ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...