266 search results - page 2 / 54 » Common-Case Computation: A High-Level Technique for Power an... |
VLSID
2009
IEEE
14 years 6 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Clock selection has a significant impact on the performance and quality of designs in high-level synthesis. In most synthesis systems, a convenient value of the clock is chosen or...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
Temperature is becoming a first rate design criterion in ASICs due to its negative impact on leakage power, reliability, performance, and packaging cost. Incorporating awareness o...
SASO
2008
IEEE
13 years 11 months ago
2008
IEEE
—High level languages greatly increase the power of a programmer at the cost of programs that consume more s than those written at a lower level of abstraction. This inefficienc...
ISLPED
2003
ACM
13 years 10 months ago
2003
ACM
This paper proposes two very fast graph theoretic heuristics for the low power binding problem given fixed number of resources and multiple architectures for the resources. First...