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» Communication latency aware low power NoC synthesis
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ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
13 years 10 months ago
Interconnect-Aware Coherence Protocols for Chip Multiprocessors
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
Liqun Cheng, Naveen Muralimanohar, Karthik Ramani,...
ASPDAC
2009
ACM
117views Hardware» more  ASPDAC 2009»
13 years 9 months ago
Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications
– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Mo...
Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
CODES
2005
IEEE
13 years 10 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...
MOBIHOC
2003
ACM
14 years 4 months ago
SHORT: self-healing and optimizing routing techniques for mobile ad hoc networks
On demand routing protocols provide scalable and costeffective solutions for packet routing in mobile wireless ad hoc networks. The paths generated by these protocols may deviate ...
Chao Gui, Prasant Mohapatra