Dynamically reconfigurable on-chip communication architectures for multi use-case chip multiprocessor applications

– The phenomenon of digital convergence and increasing application complexity today is motivating the design of chip multiprocessor (CMP) applications with multiple use cases. Most traditional on-chip communication architecture design techniques perform synthesis and optimization only for a single use-case, which may lead to sub-optimal design decisions for multi-use case applications. In this paper we present a framework to generate a dynamically reconfigurable crossbarbased on-chip communication architecture that can support multiple use-case bandwidth and latency constraints. Our framework generates on-chip communication architectures with a low cost, low power dissipation, and with minimal reconfiguration overhead. Results of applying our framework on several networking CMP applications show that our approach is able to generate a crossbar solution with significantly lower cost (2.4× to 3.8×), and lower power

• Type: Conference
• Year: 2009
• Where: ASPDAC
• Authors: Sudeep Pasricha, Nikil Dutt, Fadi J. Kurdahi
• Keywords: ASPDAC 2009, Crossbarbased On-chip Communication, On-chip Communication Architectures, Traditional On-chip Communication