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» Compact modelling of Through-Silicon Vias (TSVs) in three-di...
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ISPD
2011
ACM
253views Hardware» more  ISPD 2011»
12 years 7 months ago
Assembling 2D blocks into 3D chips
Three-dimensional ICs promise to significantly extend the scale of system integration and facilitate new-generation electronics. However, progress in commercial 3D ICs has been s...
Johann Knechtel, Igor L. Markov, Jens Lienig
DAC
2010
ACM
13 years 8 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
ICCAD
2004
IEEE
138views Hardware» more  ICCAD 2004»
14 years 1 months ago
A thermal-driven floorplanning algorithm for 3D ICs
As the technology progresses, interconnect delays have become bottlenecks of chip performance. Three dimensional (3D) integrated circuits are proposed as one way to address this p...
Jason Cong, Jie Wei, Yan Zhang
ASAP
2011
IEEE
233views Hardware» more  ASAP 2011»
12 years 4 months ago
Accelerating vision and navigation applications on a customizable platform
—The domain of vision and navigation often includes applications for feature tracking as well as simultaneous localization and mapping (SLAM). As these problems require computati...
Jason Cong, Beayna Grigorian, Glenn Reinman, Marco...