229 search results - page 2 / 46 » Compaction Schemes with Minimum Test Application Time |
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
SODA
1998
ACM
13 years 6 months ago
1998
ACM
Given an undirected graph with nonnegative costs on the edges, the routing cost of any of its spanning trees is the sum over all pairs of vertices of the cost of the path between t...
FUN
2010
Springer
13 years 9 months ago
2010
Springer
The way memory hierarchy has evolved in recent decades has opened new challenges in the development of indexing structures in general and spatial access methods in particular. In t...
VLSID
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...