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PATMOS
2004
Springer
13 years 11 months ago
Leakage Power Analysis and Comparison of Deep Submicron Logic Gates
Basic combinational gates, including NAND, NOR and XOR, are fundamental building blocks in CMOS digital circuits. This paper analyses and compares the power consumption due to tran...
Geoff V. Merrett, Bashir M. Al-Hashimi
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 3 days ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
ICPPW
2009
IEEE
13 years 3 months ago
A Scalable Parallel Approach for Peptide Identification from Large-Scale Mass Spectrometry Data
Identifying peptides, which are short polymeric chains of amino acid residues in a protein sequence, is of fundamental importance in systems biology research. The most popular appr...
Gaurav Ramesh Kulkarni, Ananth Kalyanaraman, Willi...
DAC
2002
ACM
14 years 6 months ago
Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver
We propose Satisfiability Checking (SAT) techniques that lead to a consistent performance improvement of up to 3x over state-ofthe-art SAT solvers like Chaff on important problem ...
Malay K. Ganai, Pranav Ashar, Aarti Gupta, Lintao ...
ASPDAC
2009
ACM
152views Hardware» more  ASPDAC 2009»
14 years 8 days ago
A novel Toffoli network synthesis algorithm for reversible logic
—Reversible logic studies have promising potential on energy lossless circuit design, quantum computation, nanotechnology, etc. Reversible logic features a one-to-one input outpu...
Yexin Zheng, Chao Huang