3 search results - page 1 / 1 » Comparing simulation techniques for microarchitecture-aware ... |
ISPASS
2006
IEEE
13 years 11 months ago
2006
IEEE
— Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
In this paper, we present DeFer -- a fast, high-quality and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a non-slicing floorplan by compacting a slicing fl...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Since across-chip interconnect delays can exceed a clock cycle in nanometer technologies, it has become essential in high performance designs to add flip-flops on wires with multi...