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» Compiler Technology for Two Novel Computer Architectures
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SIGPLAN
2008
13 years 5 months ago
A parallel dynamic compiler for CIL bytecode
Multi-core technology is being employed in most recent high-performance architectures. Such architectures need specifically designed multi-threaded software to exploit all the pot...
Simone Campanoni, Giovanni Agosta, Stefano Crespi-...
HPCA
2009
IEEE
14 years 5 months ago
A novel architecture of the 3D stacked MRAM L2 cache for CMPs
Magnetic Random Access Memory (MRAM) is considered to be a promising future memory technology due to its low leakage power, high density and fast read speed. The heterogeneous int...
Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yira...
HPCN
1998
Springer
13 years 9 months ago
Evaluation of Two Compiler-Based Approaches for the Parallelisation of an MPEG-2 Decoder
In this paper, we evaluate two different approaches for the compiler-based parallelisation of a C program for MPEG-2 decoding. The first approach experiments with a commercial auto...
Arnaud Laffitte, Rizos Sakellariou, John R. Gurd
DAC
2003
ACM
13 years 10 months ago
Instruction set compiled simulation: a technique for fast and flexible instruction set simulation
Instruction set simulators are critical tools for the exploration and validation of new programmable architectures. Due to increasing complexity of the architectures and timeto-ma...
Mehrdad Reshadi, Prabhat Mishra, Nikil D. Dutt
IEEECIT
2010
IEEE
13 years 3 months ago
Applying Two New Methods to the Teaching of Computer Architecture
In undergraduate teaching, Computer Architecture (CA) is one of the courses with more systematic, nsive and abstract knowledge. In current Chinese universities, how to bring up und...
Zhigang Gao, Ganggang Xue, Guojun Dai, Xuehui Wei