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IPPS
1998
IEEE
13 years 9 months ago
Compiler-Optimization of Implicit Reductions for Distributed Memory Multiprocessors
This paper presents reduction recognition and parallel code generationstrategies for distributed-memorymultiprocessors. We describe techniques to recognize a broad range of implic...
Bo Lu, John M. Mellor-Crummey
IEEEPACT
1998
IEEE
13 years 9 months ago
Parallelization of Benchmarks for Scalable Shared-Memory Multiprocessors
This work identifies practical compiling techniques for scalable shared memory machines. For this, we have focused on experimental studies using a real machine and representative ...
Yunheung Paek, Angeles G. Navarro, Emilio L. Zapat...
DAC
2002
ACM
14 years 6 months ago
Exploiting shared scratch pad memory space in embedded multiprocessor systems
In this paper, we present a compiler strategy to optimize data accesses in regular array-intensive applications running on embedded multiprocessor environments. Specifically, we p...
Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhar...
IPPS
2002
IEEE
13 years 10 months ago
Implementing the NAS Benchmark MG in SAC
SAC is a purely functional array processing language designed with numerical applications in mind. It supports generic, high-level program specifications in the style of APL. How...
Clemens Grelck
ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
13 years 11 months ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman