Sciweavers

82 search results - page 15 / 17
» Compiling Ruby into FPGAs
Sort
View
ARC
2006
Springer
124views Hardware» more  ARC 2006»
13 years 9 months ago
A Flexible Multi-port Caching Scheme for Reconfigurable Platforms
Abstract. Memory accesses contribute sunstantially to aggregate system delays. It is critical for designers to ensure that the memory subsystem is designed efficiently, and much wo...
Su-Shin Ang, George A. Constantinides, Peter Y. K....
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
13 years 9 months ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
JUCS
2007
108views more  JUCS 2007»
13 years 5 months ago
On Pipelining Sequences of Data-Dependent Loops
: Sequences of data-dependent tasks, each one traversing large data sets, exist in many applications (such as video, image and signal processing applications). Those tasks usually ...
Rui Rodrigues, João M. P. Cardoso
TVLSI
2010
13 years 15 hour ago
Improving FPGA Performance for Carry-Save Arithmetic
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP...
Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk,...
ASPDAC
2012
ACM
253views Hardware» more  ASPDAC 2012»
12 years 1 months ago
An integrated and automated memory optimization flow for FPGA behavioral synthesis
Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong