511 search results - page 4 / 103 » Compiling for instruction cache performance on a multithread... |
JUCS
2000
13 years 5 months ago
2000
: This paper presents an evaluation of our Scheduled Dataflow (SDF) Processor. Recent focus in the field of new processor architectures is mainly on VLIW (e.g. IA-64), superscalar ...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
Energy consumption is of significant concern in battery operated embedded systems. In the processors of such systems, the instruction cache consumes a significant fraction of the ...
DAC
2010
ACM
13 years 6 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the per...
JUCS
2000
13 years 5 months ago
2000
: Since the era of vector and pipelined computing, the computational speed is limited by the memory access time. Faster caches and more cache levels are used to bridge the growing ...
SAC
2006
ACM
13 years 11 months ago
2006
ACM
Esterel is a concurrent synchronous language for developing reactive systems. As an alternative to the classical software and hardware synthesis paths, the reactive processing app...