271 search results - page 1 / 55 » Complexity-Effective Superscalar Processors |
ISCA
1997
IEEE
13 years 9 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
ARCS
2010
Springer
13 years 9 months ago
2010
Springer
Register renaming is a widely used technique to remove false data dependencies in contemporary superscalar microprocessors. The register rename logic includes a mapping table that ...
IEEEPACT
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper explores microarchitecture models for a simultaneous multithreaded processor with multimedia enhancements. We enhance a wide-issue superscalar processor by the simultan...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
DSN
2008
IEEE
13 years 11 months ago
2008
IEEE
Conventional processor fault tolerance based on time/space redundancy is robust but prohibitively expensive for commodity processors. This paper explores an unconventional approac...