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» Component-Wise Instruction-Cache Behavior Prediction
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ATVA
2004
Springer
117views Hardware» more  ATVA 2004»
13 years 10 months ago
Component-Wise Instruction-Cache Behavior Prediction
nded Abstract – Oleg Parshin∗ Abdur Rakib† Stephan Thesing∗ Reinhard Wilhelm∗ The precise determination of worst-case execution times (WCETs) for programs is mostly bein...
Abdur Rakib, Oleg Parshin, Stephan Thesing, Reinha...
DAC
2012
ACM
11 years 7 months ago
WCET-centric partial instruction cache locking
Caches play an important role in embedded systems by bridging the performance gap between high speed processors and slow memory. At the same time, caches introduce imprecision in ...
Huping Ding, Yun Liang, Tulika Mitra
ISORC
2007
IEEE
13 years 11 months ago
Time-Predictable Task Preemption for Real-Time Systems with Direct-Mapped Instruction Cache
Modern processors used in embedded systems are becoming increasingly powerful, having features like caches and pipelines to speedup execution. While execution speed of embedded so...
Raimund Kirner, Peter P. Puschner
RTSS
1994
IEEE
13 years 9 months ago
Bounding Worst-Case Instruction Cache Performance
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
CASES
2001
ACM
13 years 8 months ago
Energy-efficient instruction cache using page-based placement
Energy consumption is a crucial factor in designing batteryoperated embedded and mobile systems. The memory system is a major contributor to the system energy in such environments...
Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. K...