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POPL
2009
ACM
14 years 6 months ago
Feedback-directed barrier optimization in a strongly isolated STM
Speed improvements in today's processors have largely been delivered in the form of multiple cores, increasing the importance of ions that ease parallel programming. Software...
Nathan Grasso Bronson, Christos Kozyrakis, Kunle O...
IPPS
2010
IEEE
13 years 3 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
BTW
2005
Springer
177views Database» more  BTW 2005»
13 years 11 months ago
Composing Web Services Specifications: Experiences in Implementing Policy-Driven Transactional Processes
: The Web Services architecture defines various specifications that applications may wish to use in combination. In this paper, we investigate the composition of the Web services s...
Stefan Tai
HIPEAC
2009
Springer
13 years 10 months ago
Steal-on-Abort: Improving Transactional Memory Performance through Dynamic Transaction Reordering
Abstract. In transactional memory, aborted transactions reduce performance, and waste computing resources. Ideally, concurrent execution of transactions should be optimally ordered...
Mohammad Ansari, Mikel Luján, Christos Kots...
EUROPAR
2007
Springer
14 years 3 days ago
Hardware Transactional Memory with Operating System Support, HTMOS
Abstract. Hardware Transactional Memory (HTM) gives software developers the opportunity to write parallel programs more easily compared to any previous programming method, and yiel...
Sasa Tomic, Adrián Cristal, Osman S. Unsal,...