28 search results - page 2 / 6 » Compressed Code Execution on DSP Architectures |
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
— The growing use of digital signal processors (DSPs) in embedded systems necessitates the use of optimizing compilers supporting their special architecture features. Beside the ...
PLDI
1999
ACM
13 years 9 months ago
1999
ACM
This paper explores compiler techniques for reducing the memory needed to load and run program executables. In embedded systems, where economic incentives to reduce both ram and r...
IPPS
2002
IEEE
13 years 10 months ago
2002
IEEE
Short vector SIMD instructions on recent microprocessors, such as SSE on Pentium III and 4, speed up code but are a major challenge to software developers. We present a compiler t...
LCTRTS
1999
Springer
13 years 9 months ago
1999
Springer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...