An Efficient VLIW DSP Architecture for Baseband Processing

The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate – the dramatically growing complexity in the register file (RF), and the poor code density. In this paper, we propose a novel ringstructure RF, which partitions the centralized RF into 2N subblocks with an explicit N-by-N switch network for N FU. Each sub-block only requires access ports for a single FU. We also propose the hierarchical VLIW encoding with variable-length RISC-like instructions and NOP removal. The ring-structure

• Type: Conference
• Year: 2003
• Where: ICCD
• Authors: Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
• Keywords: Hardware, Hierarchical Vliw, ICCD 2003, Variable-length Risc-like Instructions, VLIW Processors