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ICCD
2003
IEEE

An Efficient VLIW DSP Architecture for Baseband Processing

14 years 16 days ago
An Efficient VLIW DSP Architecture for Baseband Processing
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major weaknesses in VLIW processors prevent the integration of more functional units (FU) for a higher instruction issuing rate – the dramatically growing complexity in the register file (RF), and the poor code density. In this paper, we propose a novel ringstructure RF, which partitions the centralized RF into 2N subblocks with an explicit N-by-N switch network for N FU. Each sub-block only requires access ports for a single FU. We also propose the hierarchical VLIW encoding with variable-length RISC-like instructions and NOP removal. The ring-structure
Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2003
Where ICCD
Authors Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen
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