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» Compressing Functional Tests for Microprocessors
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ATS
2005
IEEE
121views Hardware» more  ATS 2005»
13 years 10 months ago
Compressing Functional Tests for Microprocessors
In the past, test data volume reduction techniques have concentrated heavily on scan test data content. However, functional vectors continue to be utilized because they target uni...
Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas ...
DCC
2008
IEEE
13 years 6 months ago
Design and Implementation of a High-Performance Microprocessor Cache Compression Algorithm
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
Xi Chen, Lei Yang, Haris Lekatsas, Robert P. Dick,...
TVLSI
2010
12 years 11 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...
DATE
2006
IEEE
78views Hardware» more  DATE 2006»
13 years 11 months ago
Functional constraints vs. test compression in scan-based delay testing
We present an approach to prevent overtesting in scan-based delay test. The test data is transformed with respect to functional constraints while simultaneously keeping as many po...
Ilia Polian, Hideo Fujiwara