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ARITH
2007
IEEE
13 years 9 months ago
A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format
The IEEE Standard 754-1985 for Binary Floating-Point Arithmetic [1] was revised [2], and an important addition is the definition of decimal floating-point arithmetic. This is inte...
Marius Cornea, Cristina Anderson, John Harrison, P...
ARITH
1999
IEEE
13 years 10 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...
ARITH
2007
IEEE
14 years 3 days ago
Optimistic Parallelization of Floating-Point Accumulation
Abstract— Floating-point arithmetic is notoriously nonassociative due to the limited precision representation which demands intermediate values be rounded to fit in the availabl...
Nachiket Kapre, André DeHon
COMGEO
2006
ACM
13 years 5 months ago
Inner and outer rounding of Boolean operations on lattice polygonal regions
Robustness problems due to the substitution of the exact computation on real numbers by the rounded floating point arithmetic are often an obstacle to obtain practical implementat...
Olivier Devillers, Philippe Guigue
ISCAS
2006
IEEE
107views Hardware» more  ISCAS 2006»
13 years 11 months ago
A versatile computation module for adaptable multimedia processors
—This paper describes a low cost, low power, versatile computation module that can be used as a coarse-grain building block in multimedia processors. The module, which has a data...
Yunan Xiang, R. Pettibon, Martin Margala