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DAC
1997
ACM
13 years 9 months ago
System-Level Synthesis of Low-Power Hard Real-Time Systems
We present a system-level approach for power optimization under a set of user specified costs and timing constraints of hard real-time designs. The approach optimizes all three d...
Darko Kirovski, Miodrag Potkonjak
MICRO
2003
IEEE
166views Hardware» more  MICRO 2003»
13 years 10 months ago
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pa...
JCSC
2002
129views more  JCSC 2002»
13 years 5 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
DAC
2006
ACM
14 years 6 months ago
Optimality study of resource binding with multi-Vdds
Deploying multiple supply voltages (multi-Vdds) on one chip is an important technique to reduce dynamic power consumption. In this work we present an optimality study for resource...
Deming Chen, Jason Cong, Yiping Fan, Junjuan Xu