Leakage Current Reduction in VLSI Systems

9 years 11 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits remain in stand-by (or sleep) mode significantly longer than in active mode, their stand-by current, and not their active switching current, determines their battery life. Hence, stringent specifications are being placed on the stand-by (or leakage) current drawn by such devices. As the power supply voltage is reduced, the threshold voltage of transistors is scaled down to maintain a constant switching speed. Since reducing the threshold voltage increases the leakage of a device exponentially, leakage current has become a dominant factor in the design of VLSI circuits. In this paper, we describe a method that uses simultaneous dynamic voltage scaling (DVS) and adaptive body biasing (ABB) to reduce the total power consumption of a processor under dynamic computational workloads. Analytical models of the leakage ...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K
Added 22 Dec 2010
Updated 22 Dec 2010
Type Journal
Year 2002
Where JCSC
Authors David Blaauw, Steven M. Martin, Trevor N. Mudge, Krisztián Flautner
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