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» Concurrent Error Detection, Diagnosis, and Fault Tolerance f...
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DFT
2003
IEEE
117views VLSI» more  DFT 2003»
13 years 10 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
ISCA
2009
IEEE
199views Hardware» more  ISCA 2009»
13 years 12 months ago
SigRace: signature-based data race detection
Detecting data races in parallel programs is important for both software development and production-run diagnosis. Recently, there have been several proposals for hardware-assiste...
Abdullah Muzahid, Darío Suárez Graci...