16 search results - page 1 / 4 » Concurrent Specification and Timing Analysis of Digital Hard... |
IPPS
2000
IEEE
13 years 9 months ago
2000
IEEE
EURODAC
1994
IEEE
13 years 9 months ago
1994
IEEE
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
SIGSOFT
2002
ACM
14 years 5 months ago
2002
ACM
We propose a unifying framework for model-based specification notations. Our framework captures the execution semantics that are common among model-based notations, and leaves the...
ICCAD
1999
IEEE
13 years 9 months ago
1999
IEEE
This paper presents a new method to synthesize timed asynchronous circuits directly from the specification without generating a state graph. The synthesis procedure begins with a ...
ACSD
2008
IEEE
13 years 7 months ago
2008
IEEE
We present a process algebra with conditionally distributed discrete-time delays and generally-distributed stochastic delays. The treatment allows for expansion laws for the paral...